홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 오디오 및 레이더 DSP SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
오디오 및 레이더 DSP SoC

TMS320C5515

활성

저전력 C55x 고정 소수점 DSP - 최대 120MHz, USB, LDC 인터페이스, FFT HWA, SAR ADC

지금 주문
데이터 시트
정오표

TMS320C5515

활성
데이터 시트 지금 주문

제품 상세 정보

CPU 16-bit Frequency (MHz) 100, 240 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
CPU 16-bit Frequency (MHz) 100, 240 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
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39개 모두 보기
유형 직함 날짜
* Data sheet TMS320C5515 Fixed-Point Digital Signal Processor datasheet (Rev. F) 2013/10/21
* Errata TMS320C5515/C5514 Fixed-Point DSP Silicon Errata (Silicon Revision 2.0) (Rev. D) 2015/07/15
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/05/19
Application note Using the TMS320C5515/14/05/04 Bootloader (Rev. D) 2019/11/25
Application note TMS320C5505/15/35/45 schematic checklist PDF | HTML 2019/02/14
Application note MEMS Microphone Direct PDM Input via I2S to a C5515 EVM With Software Decimation 2016/09/22
Application note Usage Guidelines for C55x On-Chip Low Dropout Regulators (LDOs) 2016/07/26
Application note Power Estimation and Pwr Consumption Sum for TMS320C5504/05/14/15/32/33/34/35/45 (Rev. A) 2016/04/04
Application note Instructions to Benchmark C55 DSP Library 2016/04/01
Application note C5000 DSP-Based Low-Power System Design 2015/11/30
User guide TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 2015/09/30
Application note Migrating from TMS320C5515 to 5517 2014/04/02
User guide TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (Rev. A) 2013/10/03
Application note FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 2013/01/09
User guide TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 2012/11/18
User guide TMS320C5515/14/05/04 DSP Real-Time Clock (RTC) User's Guide (Rev. A) 2012/11/15
User guide TMS320C5515 DSP System User's Guide (Rev. E) 2012/09/14
User guide TMS320C5515/14/05/04 DSP Inter-IC Sound (I2S) Bus User's Guide (Rev. B) 2012/08/09
User guide TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (Rev. A) 2012/03/07
User guide TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 2012/01/13
Application note Migrating from TMS320C5515/05 to TMS320C5535/34/33/32 (Rev. A) 2011/12/22
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011/12/15
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011/11/09
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011/11/09
Product overview C5515 eZdsp (Rev. A) 2010/11/08
Product overview TMS320C5514 and TMS320C5515 DSP Product Bulletin 2010/01/18
Product overview Low-power Signal Chain Solutions Based on C5515 DSP 2010/01/12
Product overview TMS320C5504, TMS320C5505, TMS320C5515 and TMS320C5514 Product Bulletin 2010/01/12
User guide TMS320C5515/05/VC05 DSP Liquid Crystal Display Controller User's Guide 2009/09/21
User guide TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output User's Guide 2009/09/21
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Inter-Integrated Circuit (I2C) Peripheral UG (Rev. A) 2009/09/21
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Serial Peripheral Interface (SPI) UG 2009/09/21
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide 2009/09/21
User guide TMS320C5515/14/05/04/VC05/VC04 DSP UART User's Guide 2009/09/21
User guide TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009/06/24
User guide TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009/06/24
User guide TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 2009/06/17
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. H) 2004/07/31
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. F) 2003/12/31

설계 및 개발

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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다.  XDS200은 저가형인 XDS110 및 고성능인 XDS560v2와 비교해 저렴한 가격대와 우수한 성능을 갖춘 균형 잡힌 제품입니다.  이 장치는 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.  핀을 통한 코어 추적의 경우 XDS560v2 (...)

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TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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디버그 프로브

LB-3P-TRACE32-DSP — DSP(디지털 신호 프로세서)용 Lauterbach TRACE32 디버그 및 트레이스 시스템

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

발송: Lauterbach GmbH
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애플리케이션 소프트웨어 및 프레임워크

C55X-USBAUDIO — C55x USB Audio Class Framework

The TMS320C55x™ Connected Audio Framework provides a software framework which allows the C55x devices to operate as a USB Audio peripheral. In addition to providing this capability, the framework can be extended by users by the incorporation of audio processing algorithms in the record and (...)
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
오디오 및 레이더 DSP SoC
TMS320C5504 — 저전력 C55x 고정 소수점 DSP - 최대 150MHz, USB TMS320C5505 — 저전력 C55x 고정 소수점 DSP - 최대 150MHz, USB, LCD 인터페이스, FFT HWA, SAR ADC TMS320C5514 — 저전력 C55x 고정 소수점 DSP - 최대 120MHz, USB TMS320C5515 — 저전력 C55x 고정 소수점 DSP - 최대 120MHz, USB, LDC 인터페이스, FFT HWA, SAR ADC
다운로드 옵션
드라이버 또는 라이브러리

SPRC100 — TMS320C55x DSP 라이브러리(DSPLIB)

DSP 라이브러리(DSPLIB)는 C55x DSP 플랫폼을 위한 최적화된 고수준 DSP 기능 모듈 모음입니다. 이 소스 코드 라이브러리에는 C55x DSP로 이식된 일반 신호 처리 수학 및 벡터 함수를 위한 C-호출 가능 함수(ANSI-C 언어 호환)가 포함되어 있습니다. 기능 섹션에 나열된 기능은 C55x DSP에 맞게 특별히 최적화되었습니다.

사용 설명서: PDF
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드라이버 또는 라이브러리

SPRC133 — TMS320C55x 칩 지원 라이브러리(CSL) – 표준 및 저전력

C55x CSL(칩 지원 라이브러리)은 사용 편의성, 다양한 C55x 장치 간 호환성 및 하드웨어 추상화를 위해 DSP 온칩 주변 기기를 구성하고 제어하는 데 사용되는 API(애플리케이션 프로그래밍 인터페이스)를 제공합니다. CSL은 표준화 및 이식성을 제공하여 개발 시간을 단축합니다.
  • C55x CSL(SPRC133): 기능 섹션에 나열된 기능은 C5501, C5502, C5509, C5509A 및 C5510, C5510A를 비롯한 TMS320C55x DSP를 위해 특별히 설계되었습니다.
  • C55x CSL - 초저전력: 기능 섹션에 (...)
사용 설명서: PDF
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드라이버 또는 라이브러리

SPRC264 — TMS320C5000/6000 IMGLIB(이미지 라이브러리)

C5000/6000 이미지 처리 라이브러리(IMGLIB)는 C 프로그래머를 위한 최적화된 이미지/비디오 처리 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 이미지/비디오 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. IMGLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.


벤치마크 확인: DSP 코어 벤치마크

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드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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소프트웨어 코덱

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VoIP, 음성 및 오디오 코덱

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
발송: Adaptive Digital Technologies, Inc.
파트너 사이트 방문
소프트웨어 코덱

ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP 텔레콤 및 오디오 코덱

Algotron provides C5000 DSP software modules for telecoms & audio. Examples are: modem data pumps, speech coders, signal generators & detectors for DTMF and caller ID. All modules feature simple yet flexible interfaces with full re-entrancy. They come with user's guides, example (...)
발송: Algotron
파트너 사이트 방문
소프트웨어 코덱

C55XCODECS — 코덱 - C55x 디바이스에 최적화

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
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소프트웨어 코덱

DSPI-3P-DSPVOIPCODECS — DSP 혁신: DSP VoIP 코덱

DSP Innovations is a supplier of C5000TM DSP-software and engineering services. Proprietary and standard vocoders from DSPINI have superior characteristics, operate in range from 300 bps up to 64 kbps and are used in: secure voice, software defined radio, wireless, VoIP, voice storage, and more. (...)
발송: DSP Innovations
파트너 사이트 방문
시뮬레이션 모델

C5515 ZCH BSDL Model

SPRM496.ZIP (5 KB) - BSDL Model
다운로드
시뮬레이션 모델

C5515 ZCH IBIS Model

SPRM497.ZIP (445 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZCH) 196 Ultra Librarian
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  • 납 마감/볼 재질
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