홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 차량용 운전자 지원 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
차량용 운전자 지원 SoC

TDA4VPE-Q1

활성

비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, 16 TOPS AI, C7xDSP 및 GPU를 지원하는 SoC

지금 주문
데이터 시트
사용자 가이드
정오표

TDA4VPE-Q1

활성
데이터 시트 지금 주문

제품 상세 정보

CPU 4 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Protocols Ethernet PCIe 1 PCIe Gen 3 Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
CPU 4 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Protocols Ethernet PCIe 1 PCIe Gen 3 Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (AND) 1063 729 mm² 27 x 27

Processor cores:

  • Up to Three C7x floating point, vector DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
  • Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
  • Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 2x32-b bus with inline ECC up to 34GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL-D/SIL-3
    • Hardware integrity up to ASIL-D/SIL-3for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting 4 external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
  • Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Three C7x floating point, vector DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
  • Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
  • Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 2x32-b bus with inline ECC up to 34GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL-D/SIL-3
    • Hardware integrity up to ASIL-D/SIL-3for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting 4 external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
  • Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

The TDA4VPE-Q1 TDA4APE-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VPE-Q1 TDA4APE-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VPE-Q1 TDA4APE-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate four core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VPE-Q1 TDA4APE-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VPE-Q1 TDA4APE-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VPE-Q1 TDA4APE-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VPE-Q1 TDA4APE-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate four core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VPE-Q1 TDA4APE-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
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30개 모두 보기
유형 직함 날짜
* Data sheet TDA4VPE-Q1, TDA4APE-Q1 Jacinto™ Automotive Processors datasheet (Rev. B) PDF | HTML 2025/11/03
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. B) PDF | HTML 2024/07/24
* User guide J784S4 J742S2 Technical Reference Manual (Rev. E) PDF | HTML 2025/09/18
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 2025/10/01
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 2025/09/25
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 2025/06/17
Functional safety information J784S4: TDA4VH TDA4AH TDA4VP TDA4AP SN17 SN18, J742S2: TDA4VPE TDA4APE SN16 TÜV Functional Safety Certificate 2025/06/11
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS (Rev. A) PDF | HTML 2025/05/16
User guide J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide (Rev. A) 2024/12/23
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024/08/05
User guide J784S4 J742S2 Technical Reference Manual (Rev. D) 2024/07/24
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024/06/20
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024/06/04
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 2024/05/14
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024/04/04
Technical article Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 2024/01/05
Technical article How to deliver current beyond 100 A to an ADAS processor PDF | HTML 2024/01/04
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023/11/16
White paper 고도로 통합된 프로세서를 사용해 효 율적인 에지 AI 시스템 설계 (Rev. A) PDF | HTML 2023/04/19
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023/01/09
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 2022/08/15
Application note Dual-TDA4x System Solution PDF | HTML 2022/04/29
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022/04/05
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 2022/03/29
Technical article How to simplify your embedded edge AI application development PDF | HTML 2022/01/28
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022/01/10
Application note TDA4 Flashing Techniques PDF | HTML 2021/07/08
White paper Jacinto™ 7 프로세서의 보안 구현 도구 2021/01/04
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 2020/10/22
Application note OSPI Tuning Procedure PDF | HTML 2020/07/08

설계 및 개발

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평가 보드

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지원되는 제품 및 하드웨어

제품
차량용 운전자 지원 SoC
TDA4APE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, AI 16 TOPS, C7xDSP를 지원하는 SoC TDA4VPE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, 16 TOPS AI, C7xDSP 및 GPU를 지원하는 SoC
다운로드 옵션
소프트웨어 개발 키트(SDK)

J742S2-PROCESSOR-QNX-SDK — QNX SDK for TDA4APE-Q1 and TDA4VPE-Q1

The J742S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4APE-Q1 and TDA4VPE-Q1 system-on-a-chip (SoCs) within our Jacinto™ (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
차량용 운전자 지원 SoC
TDA4APE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, AI 16 TOPS, C7xDSP를 지원하는 SoC TDA4VPE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, 16 TOPS AI, C7xDSP 및 GPU를 지원하는 SoC
다운로드 옵션
애플리케이션 소프트웨어 및 프레임워크

J742S2-SW — J742S2 software

Software packages for Processor SDK release
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
차량용 운전자 지원 SoC
TDA4APE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, AI 16 TOPS, C7xDSP를 지원하는 SoC TDA4VPE-Q1 — 비전 인식 및 분석을 위한 쿼드 Arm® Cortex®-A72, 16 TOPS AI, C7xDSP 및 GPU를 지원하는 SoC
요청
펌웨어

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 펌웨어

SecIC-HSM은 MCU/SoC 칩에 필요한 사이버 보안 요건을 충족하도록 설계되었습니다. HSM 펌웨어는 자동차, 신에너지, 태양광, 로봇 공학, 헬스케어, 항공 등의 분야에 적용될 수 있습니다. 이용 가능한 사이버 보안 기능으로는 보안 부팅, SecOC(보안 통신), 보안 진단, 보안 스토리지, 보안 업데이트, 보안 디버깅 및 키 관리 등이 있습니다. SecIC-HSM의 장점: 여러 칩 시리즈와 종합적인 소프트웨어 호환성을 지원하는 원스톱 사이버 보안 솔루션으로, 업계를 선도하는 성능을 제공하며, 약 30곳의 OEM 대량 (...)
발송: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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펌웨어

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 알고리즘 펌웨어

Uni-Sentry의 보안 솔루션은 양자 컴퓨터가 기존의 암호화 알고리즘에 미치는 복호화 위협에 맞설 수 있는 PQC 알고리즘을 채택합니다. PQC 펌웨어는 HSM(Hardware Security Module)과 공동 최적화되어 하드웨어 가속 및 보안 향상을 활용해 암호화 알고리즘 실행 효율성과 보안을 개선합니다. 


Uni-Sentry는 세계의 양자 컴퓨팅 발전 양상을 꾸준히 모니터링하여 자사 알고리즘 포트폴리오를 업데이트합니다. 현재 PQC 제품 기능의 예를 들면 다음과 같습니다:

  • SP 800-208: LMS 및 XMSS 
  • (...)
발송: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
운영 체제(OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 사전 인증 안전 RTOS

SAFERTOS®는 임베디드 프로세서를 위해 설계된 고유한 실시간 운영 체제입니다. TÜV SÜD의 IEC 61508 SIL3 및 ISO 26262 ASILD 표준에 따라 사전 인증을 받았습니다. SAFERTOS®는 WHIS 전문가 팀에서 안전을 위해 특별히 제작되었으며, 전 세계적으로 안전이 중요한 응용 분야에 사용됩니다. WHIS와 텍사스 인스트루먼트는 10년 넘게 협력해 왔습니다. 이 기간 동안, WHIS는 SAFERTOS®를 광범위한 TI 프로세서로 이식하여 널리 사용되는 모든 코어를 지원하며 요청 시 추가 아키텍처를 (...)
발송: WITTENSTEIN High Integrity Systems
파트너 사이트 방문
시뮬레이션 모델

J742S2 BSDL Model

SPRM866.ZIP (16 KB) - BSDL Model
다운로드
시뮬레이션 모델

J742S2 IBIS Model

SPRM865.ZIP (1496 KB) - IBIS Model
다운로드
시뮬레이션 모델

J742S2 Thermal Model

SPRM864.ZIP (0 KB) - Thermal Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (AND) 1063 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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