产品详情

DSP type 1 C67x DSP (max) (MHz) 167, 200, 225, 300 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C67x DSP (max) (MHz) 167, 200, 225, 300 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
BGA (ZDP) 272 729 mm² 27 x 27 HLQFP (PYP) 208 784 mm² 28 x 28 PBGA (GDP) 272 729 mm² 27 x 27 PBGA (ZDP) 272 See data sheet
  • Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B
    • Eight 32-Bit Instructions/Cycle
    • 32/64-Bit Data Word
    • 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
    • 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
    • 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS
    • Rich Peripheral Set, Optimized for Audio
    • Highly Optimized C/C++ Compiler
    • Extended Temperature Devices Available
  • Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
    • Eight Independent Functional Units:
      • 2 ALUs (Fixed-Point)
      • 4 ALUs (Floating-/Fixed-Point)
      • 2 Multipliers (Floating-/Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Native Instructions for IEEE 754
      • Single- and Double-Precision
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
  • L1/L2 Memory Architecture
    • 4K-Byte L1P Program Cache (Direct-Mapped)
    • 4K-Byte L1D Data Cache (2-Way)
    • 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
  • Two McASPs
    • Two Independent Clock Zones Each (1 TX and 1 RX)
    • Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
    • Each Clock Zone Includes:
      • Programmable Clock Generator
      • Programmable Frame Sync Generator
      • TDM Streams From 2-32 Time Slots
      • Support for Slot Size:
          8, 12, 16, 20, 24, 28, 32 Bits
      • Data Formatter for Bit Manipulation
    • Wide Variety of I2S and Similar Bit Stream Formats
    • Integrated Digital Audio Interface Transmitter (DIT) Supports:
      • S/PDIF, IEC60958-1, AES-3, CP-430 Formats
      • Up to 16 transmit pins
      • Enhanced Channel Status/User Data
    • Extensive Error Checking and Recovery
  • Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
  • Two Multichannel Buffered Serial Ports:
    • Serial-Peripheral-Interface (SPI)
    • High-Speed TDM Interface
    • AC97 Interface
  • Two 32-Bit General-Purpose Timers
  • Dedicated GPIO Module With 16 pins (External Interrupt Capable)
  • Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 208-Pin PowerPAD™ PQFP (PYP)
  • 272-BGA Packages (GDP and ZDP)
  • 0.13-µm/6-Level Copper Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.2-V Internal (GDP/ZDP/ PYP)
  • 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]

TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26-V designs.
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.
Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B.

  • Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B
    • Eight 32-Bit Instructions/Cycle
    • 32/64-Bit Data Word
    • 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
    • 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
    • 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS
    • Rich Peripheral Set, Optimized for Audio
    • Highly Optimized C/C++ Compiler
    • Extended Temperature Devices Available
  • Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
    • Eight Independent Functional Units:
      • 2 ALUs (Fixed-Point)
      • 4 ALUs (Floating-/Fixed-Point)
      • 2 Multipliers (Floating-/Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Native Instructions for IEEE 754
      • Single- and Double-Precision
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
  • L1/L2 Memory Architecture
    • 4K-Byte L1P Program Cache (Direct-Mapped)
    • 4K-Byte L1D Data Cache (2-Way)
    • 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
  • Two McASPs
    • Two Independent Clock Zones Each (1 TX and 1 RX)
    • Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
    • Each Clock Zone Includes:
      • Programmable Clock Generator
      • Programmable Frame Sync Generator
      • TDM Streams From 2-32 Time Slots
      • Support for Slot Size:
          8, 12, 16, 20, 24, 28, 32 Bits
      • Data Formatter for Bit Manipulation
    • Wide Variety of I2S and Similar Bit Stream Formats
    • Integrated Digital Audio Interface Transmitter (DIT) Supports:
      • S/PDIF, IEC60958-1, AES-3, CP-430 Formats
      • Up to 16 transmit pins
      • Enhanced Channel Status/User Data
    • Extensive Error Checking and Recovery
  • Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
  • Two Multichannel Buffered Serial Ports:
    • Serial-Peripheral-Interface (SPI)
    • High-Speed TDM Interface
    • AC97 Interface
  • Two 32-Bit General-Purpose Timers
  • Dedicated GPIO Module With 16 pins (External Interrupt Capable)
  • Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 208-Pin PowerPAD™ PQFP (PYP)
  • 272-BGA Packages (GDP and ZDP)
  • 0.13-µm/6-Level Copper Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.2-V Internal (GDP/ZDP/ PYP)
  • 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]

TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26-V designs.
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.
Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B.

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320C6713B Floating-Point Digital Signal Processor 数据表 (Rev. B) 2006年 6月 30日
* 勘误表 TMS320C6713, TMS320C6713B DSPs Silicon Errata (Silicon Revisions 2.0, 1.1) (Rev. J) 2005年 8月 12日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021年 5月 19日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
用户指南 TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) 2008年 11月 20日
应用手册 Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007年 5月 20日
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007年 4月 11日
用户指南 TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007年 3月 26日
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006年 12月 14日
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006年 11月 15日
用户指南 TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (Rev. A) 2006年 11月 7日
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006年 1月 1日
应用手册 Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H) 2005年 11月 11日
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005年 3月 1日
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005年 1月 25日
用户指南 TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. C) 2004年 8月 2日
用户指南 TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 2004年 6月 8日
应用手册 TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A) 2004年 5月 31日
用户指南 TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004年 3月 25日
应用手册 TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
应用手册 TMS320C621x/671x EDMA Performance Data 2004年 3月 5日
应用手册 TMS320C621x/TMS320C671x EDMA Architecture 2004年 3月 5日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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驱动程序或库

MATHLIB — 用于浮点器件的 DSP 数学函数库

德州仪器 (TI) 数学库是优化的浮点数学函数库,用于使用 TI 浮点器件的 C 编程器。这些例程通常用于计算密集型实时应用,最佳执行速度是这些应用的关键。通过使用这些例程(而不是在现有运行时支持中找到的例程),您可以在无需重写现有代码的情况下获得更快的执行速度。MATHLIB 库包括目前在现有实时支持库中提供的所有浮点数学例程。这些新函数可称为当前实时支持库名称或包含在数学库中的新名称。
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

启动 下载选项
仿真模型

C6713B GDP BSDL Model

SPRM214.ZIP (6 KB) - BSDL Model
仿真模型

C6713B GDP IBIS Model (Rev. B)

SPRM142B.ZIP (81 KB) - IBIS Model
仿真模型

C6713B PYP IBIS Model (Rev. B)

SPRM143B.ZIP (80 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
封装 引脚 下载
BGA (ZDP) 272 查看选项
HLQFP (PYP) 208 查看选项
PBGA (GDP) 272 查看选项
PBGA (ZDP) 272 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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