C67x floating-point DSP- up to 300MHz, McBSP, 16-Bit EMIFA
产品详细信息
参数
封装|引脚|尺寸
特性
- Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B
- Eight 32-Bit Instructions/Cycle
- 32/64-Bit Data Word
- 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
- 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
- 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS
- Rich Peripheral Set, Optimized for Audio
- Highly Optimized C/C++ Compiler
- Extended Temperature Devices Available
- Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
- Eight Independent Functional Units:
- 2 ALUs (Fixed-Point)
- 4 ALUs (Floating-/Fixed-Point)
- 2 Multipliers (Floating-/Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Independent Functional Units:
- Instruction Set Features
- Native Instructions for IEEE 754
- Single- and Double-Precision
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
- Native Instructions for IEEE 754
- L1/L2 Memory Architecture
- 4K-Byte L1P Program Cache (Direct-Mapped)
- 4K-Byte L1D Data Cache (2-Way)
- 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
- Device Configuration
- Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
- Endianness: Little Endian, Big Endian
- 32-Bit External Memory Interface (EMIF)
- Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
- 512M-Byte Total Addressable External Memory Space
- Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
- 16-Bit Host-Port Interface (HPI)
- Two McASPs
- Two Independent Clock Zones Each (1 TX and 1 RX)
- Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
- Each Clock Zone Includes:
- Programmable Clock Generator
- Programmable Frame Sync Generator
- TDM Streams From 2-32 Time Slots
- Support for Slot Size:
- 8, 12, 16, 20, 24, 28, 32 Bits
- Data Formatter for Bit Manipulation
- Wide Variety of I2S and Similar Bit Stream Formats
- Integrated Digital Audio Interface Transmitter (DIT) Supports:
- S/PDIF, IEC60958-1, AES-3, CP-430 Formats
- Up to 16 transmit pins
- Enhanced Channel Status/User Data
- Extensive Error Checking and Recovery
- Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
- Two Multichannel Buffered Serial Ports:
- Serial-Peripheral-Interface (SPI)
- High-Speed TDM Interface
- AC97 Interface
- Two 32-Bit General-Purpose Timers
- Dedicated GPIO Module With 16 pins (External Interrupt Capable)
- Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
- IEEE-1149.1 (JTAG
) Boundary-Scan-Compatible
- 208-Pin PowerPAD™ PQFP (PYP)
- 272-BGA Packages (GDP and ZDP)
- 0.13-µm/6-Level Copper Metal Process
- CMOS Technology
- 3.3-V I/Os, 1.2
-V Internal (GDP/ZDP/ PYP)
- 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26-V designs.
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B.
描述
The TMS320C67x DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).
Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).
The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.
The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel.
Limited design support from TI available
This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.
技术文档
设计与开发
有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。硬件开发
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
软件开发
特性
- 自然 C 源码
- 优化的 C 代码,具有内建运算符
- 手工编码、经汇编语言优化的例程
- C 调用的例程,可内联且与 TMS320C6000 编译器完全兼容
- 接受单样片或向量输入的例程
- 提供的函数经 C 模型和现有实时支持函数测试
- 基准(周期和代码大小)
- 使用代码生成工具 v7.2.0 进行编译
特性
Optimized DSP routines including functions for:
- Adaptive filtering
- Correlation
- FFT
- Filtering and convolution: FIR, biquad, IIR, convolution
- Math: Dot products, max value, min value, etc.
- Matrix operations
设计工具和仿真
特性
- Supports many TI processors including Sitara and Jacinto Processors and DSPs
- Search by type of product, TI devices supported, or country
- Links and contacts for quick engagement
- Third-party companies located around the world
CAD/CAE 符号
封装 | 引脚 | 下载 |
---|---|---|
(PYP) | 208 | 了解详情 |
BGA (GDP) | 272 | 了解详情 |
BGA (ZDP) | 272 | 了解详情 |
订购与质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/FIT 估算
- 材料成分
- 认证摘要
- 持续可靠性监测