TLC2578 处于停产状态
请考虑从这些替代产品中选择一款:
open-in-new 比较替代产品
功能与比较器件相似
ADS8668 正在供货 采用 5V 电源并具有双极性输入的 12 位、500kSPS 8 通道 SAR ADC Higher speed

产品详情

Resolution (Bits) 12 Sample rate (max) (ksps) 200 Number of input channels 8 Interface type SPI Architecture SAR Input type Pseudo-Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 10 Input voltage range (min) (V) -10 Features Oscillator Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 29 Analog supply (min) (V) 4.75 Analog supply voltage (max) (V) 5.5 SNR (dB) 72 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
Resolution (Bits) 12 Sample rate (max) (ksps) 200 Number of input channels 8 Interface type SPI Architecture SAR Input type Pseudo-Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 10 Input voltage range (min) (V) -10 Features Oscillator Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 29 Analog supply (min) (V) 4.75 Analog supply voltage (max) (V) 5.5 SNR (dB) 72 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
  • Maximum Throughput 200-KSPS
  • Multiple Analog Inputs:
    • 8 Single-Ended Channels for TLC3578/2578
    • 4 Single-Ended Channels for TLC3574/2574
  • Analog Input Range: ±10 V
  • Pseudodifferential Analog Inputs
  • SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
  • Built-In Conversion Clock and 8x FIFO
  • Single 5-V Analog Supply; 3-/5-V Digital Supply
  • Low-Power
    • 5.8 mA in Normal Operation
    • 20 µA in Power Down
  • Programmable Autochannel Sweep and Repeat
  • Hardware-Controlled, Programmable Sampling Period
  • Hardware Default Configuration
  • INL: TLC3574/78: ±1 LSB;
            TLC2574/78: ±0.5 LSB
  • DNL: TLC3574/78: ±0.5 LSB;
              TLC2574/78: ±0.5 LSB
  • SINAD: TLC3574/78: 79 dB;
              TLC2574/78: 72 dB
  • THD: TLC3574/78: –82 dB;
              TLC2574/78: –82 dB

Note: Recommended Voltage Reference: REF02 and REF102

  • 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
  • Maximum Throughput 200-KSPS
  • Multiple Analog Inputs:
    • 8 Single-Ended Channels for TLC3578/2578
    • 4 Single-Ended Channels for TLC3574/2574
  • Analog Input Range: ±10 V
  • Pseudodifferential Analog Inputs
  • SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
  • Built-In Conversion Clock and 8x FIFO
  • Single 5-V Analog Supply; 3-/5-V Digital Supply
  • Low-Power
    • 5.8 mA in Normal Operation
    • 20 µA in Power Down
  • Programmable Autochannel Sweep and Repeat
  • Hardware-Controlled, Programmable Sampling Period
  • Hardware Default Configuration
  • INL: TLC3574/78: ±1 LSB;
            TLC2574/78: ±0.5 LSB
  • DNL: TLC3574/78: ±0.5 LSB;
              TLC2574/78: ±0.5 LSB
  • SINAD: TLC3574/78: 79 dB;
              TLC2574/78: 72 dB
  • THD: TLC3574/78: –82 dB;
              TLC2574/78: –82 dB

Note: Recommended Voltage Reference: REF02 and REF102

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host.

In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host.

In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 3
类型 标题 下载最新的英语版本 日期
* 数据表 5-V Analog, 3-/5-V Digital, 14-/12-Bit, 200-KSPS, 4-/8-Channel Serial Analog-to- 数据表 (Rev. C) 2003年 5月 29日
电子书 Best of Baker's Best: Precision Data Converters -- SAR ADCs 2015年 5月 21日
应用手册 Determining Minimum Acquisition Times for SAR ADCs, part 2 2011年 3月 17日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

仿真模型

TLC2578 IBIS Model

SLAM136.ZIP (53 KB) - IBIS Model
计算工具

ANALOG-ENGINEER-CALC — 模拟工程师计算器

模拟工程师计算器旨在加快模拟电路设计工程师经常使用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算的列表(从使用反馈电阻器设置运算放大器增益到为稳定模数转换器 (ADC) 驱动器缓冲器电路选择合适的电路设计元件)。除了可用作单独的工具之外,该计算器还能够很好地与模拟工程师口袋参考书中所述的概念配合使用。
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
模拟工具

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能,允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装,如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能,但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表,请参阅:SpiceRack - 完整列表 

需要 HSpice (...)

用户指南: PDF
下载英文版本 (Rev.A): PDF
封装 引脚 下载
SOIC (DW) 24 查看选项
TSSOP (PW) 24 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频