SN74S1053

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16 位肖特基屏障二极管总线终端阵列

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数据表

document-pdfAcrobat SN74S1053 数据表 (Rev. A) (英语)

SN74S1053

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数据表

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Technology family

S

Bits (#)

16

Rating

Catalog

Operating temperature range (°C)

0 to 70

Technology family

S

Bits (#)

16

Rating

Catalog

Operating temperature range (°C)

0 to 70

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

PDIP (N)

20

228.702 mm² (24.33 mm × 9.4 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200mA
16-Bit Array Structure Suited for Bus-Oriented Systems
Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200mA
16-Bit Array Structure Suited for Bus-Oriented Systems
Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 16-bit high-speed Schottky diode array suitable for clamping to V_CC and/or GND.

The SN74S1053 is characterized for operation from 0°C to 70°C.

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 16-bit high-speed Schottky diode array suitable for clamping to V_CC and/or GND.

The SN74S1053 is characterized for operation from 0°C to 70°C.

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	SN74S1053 数据表 (Rev. A)				1997-8-1

SN74S1053

16 位肖特基屏障二极管总线终端阵列

SN74S1053

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