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D 型锁存器

SN74LVCH16373A

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SN74LVCH16373A

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产品详情

Number of channels 16 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 16 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • Member of the Texas Instruments Widebus Family
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for External Pull-up or Pull-down Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Member of the Texas Instruments Widebus Family
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for External Pull-up or Pull-down Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVCH16373A 16-Bit Transparent D-Type Latch With 3-State Outputs 数据表 (Rev. N) PDF | HTML 2014-7-24
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17

设计与开发

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仿真模型

SN74LVCH16373A IBIS Model (Rev. B)

SCEM077A (12 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
SSOP (DL) 48 Ultra Librarian
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