SN74LVCH16244A
- Member of the Texas Instruments
Widebus Family - Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.1 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection - Supports Mixed-Mode Signal Operation on All Ports
(5-V Input or Output Voltage With 3.3-V VCC) - Bus Hold on Data Inputs Eliminates the Need for
External Pullup or Pulldown Resistors - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
The SN74LVCH16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
技术文档
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN74LVCH16244A 16-Bit Buffer/Driver With 3-State Outputs 数据表 (Rev. B) | PDF | HTML | 2013-11-7 | ||
| 应用手册 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018-9-17 | ||||
| 应用手册 | Simultaneous-Switching Performance of TI Logic Devices (Rev. B) | 2005-2-23 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SSOP (DL) | 48 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |
| TVSOP (DGV) | 48 | Ultra Librarian |