产品详情

Technology family LVC Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 20 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 20 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.4 ns at 3.3 V
  • Output Ports Have Equivalent 26-Ω Series
    Resistors, so No External Resistors are Required
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.4 ns at 3.3 V
  • Output Ports Have Equivalent 26-Ω Series
    Resistors, so No External Resistors are Required
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH162244A device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH162244A device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs 数据表 (Rev. L) PDF | HTML 2014-5-2
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17
应用手册 Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 2005-2-23

设计与开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

仿真模型

HSPICE MODEL OF SN74LVCH162244A

SCEJ233.ZIP (293 KB) - HSpice 模型
支持的产品和硬件
仿真模型

SN74LVCH162244A Behavioral SPICE Model

SCAM096.ZIP (7 KB) - PSpice 模型
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仿真模型

SN74LVCH162244A IBIS Model (Rev. B)

SCEM063A (12 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
SSOP (DL) 48 Ultra Librarian

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