产品详细信息

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 32 ICC (Max) (uA) 10 IOH (Max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 32 ICC (Max) (uA) 10 IOH (Max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
DSBGA (YZP) 5 2 mm² .928 x 1.428 SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DPW) 5 1 mm² .8 x .8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

下载

技术文档

star = 有关此产品的 TI 精选热门文档
未找到结果。请清除搜索,并重试。
查看全部 32
类型 项目标题 下载最新的英语版本 日期
* 数据表 SN74LVC1G125 Single Bus Buffer Gate With 3-State Output 数据表 (Rev. T) PDF | HTML 21 Oct 2014
应用手册 Application Brief Enabling Optimal Solar Inverter Designs with Logic PDF | HTML 17 Aug 2021
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
选择指南 Little Logic Guide 2014 (Rev. G) 06 Jul 2018
应用手册 Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
选择指南 Logic Guide (Rev. AB) 12 Jun 2017
应用手册 How to Select Little Logic (Rev. A) 26 Jul 2016
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 17 Nov 2014
选择指南 小尺寸逻辑器件指南 (Rev. E) 下载最新的英文版本 (Rev.G) 16 Jul 2012
用户指南 LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
应用手册 CMOS 非缓冲反向器在振荡器电路中的使用 下载英文版本 23 Mar 2006
应用手册 选择正确的电平转换解决方案 (Rev. A) 下载英文版本 (Rev.A) 23 Mar 2006
更多文献资料 Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
用户指南 Signal Switch Data Book (Rev. A) 14 Nov 2003
更多文献资料 Logic Cross-Reference (Rev. A) 07 Oct 2003
用户指南 LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
应用手册 Texas Instruments Little Logic Application Report 01 Nov 2002
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
应用手册 Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
更多文献资料 STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
应用手册 LVC Characterization Information 01 Dec 1996
应用手册 Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
应用手册 Live Insertion 01 Oct 1996
设计指南 Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
应用手册 Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

评估板

5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑 EVM

灵活的 EVM 设计用于支持具有 5 至 8 引脚数且采用 DCK、DCT、DCU、DRL 或 DBV 封装的任何器件。
TI.com 無法提供
仿真模型

HSPICE Model for SN74LVC1G125

SCEJ253.ZIP (87 KB) - HSpice Model
仿真模型

SN74LVC1G125 IBIS Model (Rev. B)

SCEM270B.ZIP (53 KB) - IBIS Model
仿真模型

SN74LVC1G125 PSpice Model

SCEM579.ZIP (20 KB) - PSpice Model
仿真模型

SN74LVC1G125 Behavioral SPICE Model

SCEM639.ZIP (7 KB) - PSpice Model
许多 TI 参考设计都包括 SN74LVC1G125

通过我们的参考设计选择工具来审查并确定最适用于您应用和参数的设计。

封装 引脚数 下载
DSBGA (YZP) 5 了解详情
SC70 (DCK) 5 了解详情
SON (DRY) 6 了解详情
SON (DSF) 6 了解详情
SOT-23 (DBV) 5 了解详情
SOT-5X3 (DRL) 5 了解详情
X2SON (DPW) 5 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频