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参数

Channels (#) 2 Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 110 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) open-in-new 查找其它 D 类触发器

封装|引脚|尺寸

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new 查找其它 D 类触发器

特性

  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down
    Mode Operation
  • Latch-up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 500-V Charged-Device Model (C101)
open-in-new 查找其它 D 类触发器

描述

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.

open-in-new 查找其它 D 类触发器
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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops 数据表 2015年 3月 29日
应用手册 Power-Up Behavior of Clocked Devices 2015年 2月 6日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

评估板 下载
10
说明
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
特性
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
评估板 下载
20
说明
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
特性
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

设计工具和仿真

仿真模型 下载
SCEM476.ZIP (15 KB) - IBIS Model

CAD/CAE 符号

封装 引脚 下载
SO (NS) 14 了解详情
SOIC (D) 14 了解详情
SSOP (DB) 14 了解详情
TSSOP (PW) 14 了解详情
TVSOP (DGV) 14 了解详情
VQFN (RGY) 14 了解详情

订购与质量

支持与培训

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