SN74LV4046A

Name: SN74LV4046A
Brand: TI
SKU: SN74LV4046A
Price: 0.59 USD

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数据表

document-pdfAcrobat SN74LV4046A High-Speed CMOS Logic Phase-Locked Loop With VCO 数据表 (Rev. E) (英语) PDF | HTML

产品详情

Technology family

LV-A

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LV-A

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-40 to 85

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
Choice of Three Phase Comparators
- Exclusive OR
- Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Optimized Power-Supply Voltage Range From 3 V to 5.5 V
Wide Operating Temperature Range From –40°C to +125°C
Latch-Up Performance Exceeds 250 mA Per JESD 17

ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
Choice of Three Phase Comparators
- Exclusive OR
- Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Optimized Power-Supply Voltage Range From 3 V to 5.5 V
Wide Operating Temperature Range From –40°C to +125°C
Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.

The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.

The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.

The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.

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