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SN74LV374A-Q1

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汽车类具有三态输出的八路边沿 D 级触发器

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SN74LV374A-Q1

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产品详情

Number of channels 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 105 Rating Automotive
Number of channels 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 105 Rating Automotive
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs 数据表 (Rev. C) 2008-1-29
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15
更多文献资料 汽车逻辑器件 英语版 2014-2-5

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