SN74LV245AT
- Inputs Are TTL-Voltage Compatible
- 4.5-V to 5.5-V VCC Operation
- Typical tpd of 3.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 5 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2.3 V
at VCC = 5 V, TA = 25°C - Supports Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
您可能感兴趣的相似产品
功能优于比较器件,可直接替换
技术文档
类型 | 项目标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN74LV245AT 数据表 (Rev. D) | 2013年 8月 1日 |
设计和开发
如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。
14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM
该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
14-24-NL-LOGIC-EVM — 通用 14 至 24 引脚无铅封装评估模块
封装 | 引脚数 | 下载 |
---|---|---|
SOIC (DW) | 20 | 了解详情 |
SOP (NS) | 20 | 了解详情 |
SSOP (DB) | 20 | 了解详情 |
TSSOP (PW) | 20 | 了解详情 |
TVSOP (DGV) | 20 | 了解详情 |
VQFN (RGY) | 20 | 了解详情 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 认证摘要
- 持续可靠性监测