SN74LV126A
- 2-V to 5.5-V VCC Operation
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2.3 V at
VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection - Support Mixed-Mode Voltage Operation on All
Ports - Latch-Up Performance Exceeds 250 mA per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
The LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
技术文档
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查看全部 1 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SNx4LV126A Quadruple Bus Buffer Gates With 3-State Outputs 数据表 (Rev. I) | PDF | HTML | 2015年 2月 17日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
封装 | 引脚 | 下载 |
---|---|---|
SOIC (D) | 14 | 查看选项 |
SOP (NS) | 14 | 查看选项 |
SSOP (DB) | 14 | 查看选项 |
TSSOP (PW) | 14 | 查看选项 |
TVSOP (DGV) | 14 | 查看选项 |
订购和质量
包含信息:
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
包含信息:
- 制造厂地点
- 封装厂地点