SN74HCT652
- Operating Voltage Range of 4.5 V to 5.5 V
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 12 ns
- ±6-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Inputs Are TTL-Voltage Compatible
- Independent Registers and Enables for A and B Buses
- Multiplexed Real-Time and Stored Data
- True Data Paths
- High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads
The HCT652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. A low input level selects real-time data; a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
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功能与比较器件相同但引脚有所不同
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN54HCT652, SN74HCT652 数据表 (Rev. D) | 2003年 3月 18日 | |||
应用手册 | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||||
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应用手册 | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997年 6月 1日 | ||||
应用手册 | 使用逻辑器件进行设计 (Rev. C) | 1997年 6月 1日 | ||||
应用手册 | SN54/74HCT CMOS Logic Family Applications and Restrictions | 1996年 5月 1日 | ||||
应用手册 | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996年 4月 1日 |
设计和开发
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14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
封装 | 引脚 | 下载 |
---|---|---|
SOIC (DW) | 24 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点