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数字多路信号分离器和解码器

SN74HC138-Q1

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汽车类 3 线至 8 线解码器/多路解复用器

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SN74HC138-Q1

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数据表 立即订购

产品详情

Technology family HC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
Technology family HC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm)
  • Qualified for Automotive Applications
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
  • Qualified for Automotive Applications
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 3-Line to 8-Line Decoder/Demultiplexer 数据表 (Rev. A) 2008-9-17
应用简报 TI 逻辑系列的内插规格值 PDF | HTML PDF | HTML 2026-4-17
更多文献资料 汽车逻辑器件 英语版 2014-2-5

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