主页 逻辑和电压转换 缓冲器、驱动器和收发器 通用收发器
主页
逻辑和电压转换
缓冲器、驱动器和收发器
通用收发器

SN74F657

正在供货

具有奇偶校验发生器/校验器和三态输出的八路收发器

立即订购
数据表

SN74F657

正在供货
数据表 立即订购

产品详情

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 
  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 
open-in-new 查找其他 通用收发器
下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同且具有相同引脚
CD74ACT245 正在供货 具有三态输出的八路同向总线收发器 Higher average drive strength (24mA)

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 10
类型 标题 下载最新的英语版本 日期
* 数据表 Octal Transceiver With Parity Generator/Checker And 3-State Outputs 数据表 (Rev. A) 1993年 10月 1日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
封装 引脚 下载
SOIC (DW) 24 查看选项
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频