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SN74F112

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具有清零和预设功能的双通道 J-K 下降沿触发器

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数据表

SN74F112

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数据表 立即订购

产品详情

Number of channels 2 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 19000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, Negative edge triggered, Preset, Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 19000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, Negative edge triggered, Preset, Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C.

 

 

 

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C.

 

 

 
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SN74HC112 正在供货 具有清零和预设功能的双通道 J-K 下降沿触发器 Voltage range (2V to 6V), average drive strength (8mA), average propagation delay (20ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 数据表 (Rev. A) 1993年 10月 1日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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