产品详情

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 3000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.5 CON (typ) (pF) 14 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 12000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 3000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.5 CON (typ) (pF) 14 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 12000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) VQFN (RGY) 20 15.75 mm² (4.5 mm × 3.5 mm)
  • Undershoot Protection for Off-Isolation on A and B Ports Up to –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

  • Undershoot Protection for Off-Isolation on A and B Ports Up to –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

The SN74CBT3244C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3244C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3244C is organized as two 4-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE\ is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3244C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3244C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3244C is organized as two 4-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE\ is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74CBT3244C 数据表 (Rev. A) 2003-10-15
应用手册 选择正确的德州仪器 (TI) 信号开关 (Rev. E) PDF | HTML 英语版 (Rev.E) PDF | HTML 2022-8-5
应用手册 多路复用器和信号开关词汇表 (Rev. B) 英语版 (Rev.B) PDF | HTML 2022-3-11
应用简报 利用关断保护信号开关消除电源时序 (Rev. C) 英语版 (Rev.C) PDF | HTML 2021-10-21

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SN74CBT3244C IBIS Model

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SSOP (DBQ) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian

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