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Bits (#) 16 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.4 Vin (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Applications GPIO Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.08 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 16 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.4 Vin (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Applications GPIO Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.08 Rating Catalog Operating temperature range (°C) -40 to 85
TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Member of the Texas Instruments Widebus™ Family
  • DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

DOC and Widebus are trademarks of Texas Instruments.

  • Member of the Texas Instruments Widebus™ Family
  • DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

DOC and Widebus are trademarks of Texas Instruments.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCAH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCAH164245 is designed so that the control pins (1DIR, 2DIR, 1OE\, and 2OE\) are supplied by VCCA.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, then both ports are in the high-impedance state.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCAH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCAH164245 is designed so that the control pins (1DIR, 2DIR, 1OE\, and 2OE\) are supplied by VCCA.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, then both ports are in the high-impedance state.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74AVCAH164245 数据表 (Rev. A) 2004-5-6
应用手册 原理图检查清单 - 使用自动双向转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024-12-3
应用手册 原理图检查清单 - 使用固定或方向控制转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024-10-3
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024-7-3
选择指南 Voltage Translation Buying Guide (Rev. A) 2021-4-15

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仿真模型

HSPICE Model for SN74AVCAH164245

SCEJ143.ZIP (51 KB) - HSpice 模型
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仿真模型

SN74AVCAH164245 IBIS Model (Rev. A)

SCEM428 (288 KB) - IBIS 模型
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封装 引脚 CAD 符号、封装和 3D 模型
TVSOP (DGV) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

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