SN74ALVCH16245
- Member of the Texas Instruments Widebus™
Family - Operates From 1.65 V to 3.6 V
- Max tpd of 3 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for
External Pullup or Pulldown Resistors - Latch-Up Performance Exceeds 250 mA Per
JESD 17 - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic high or low level applied to prevent excess ICC and ICCZ.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN74ALVCH16245 16-Bit Bus Transceiver With 3-State Outputs 数据表 (Rev. M) | PDF | HTML | 2013-11-8 | ||
| 应用手册 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018-9-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SSOP (DL) | 48 | Ultra Librarian |
| TVSOP (DGV) | 48 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |