SN74ALS569A
- 3-State Q Outputs Drive Bus Lines Directly
- Counter Operation Independent of 3-State Output
- Fully Synchronous Clear, Count, and Load
- Asynchronous Clear Is Also Provided
- Fully Cascadable
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.
The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.
A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.
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技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | Synchronous 4-Bit Up/Down Decade And Binary Counters With 3-State Outputs 数据表 (Rev. A) | 1995年 1月 1日 | |||
选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
应用手册 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 | |||
用户指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
应用手册 | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||||
应用手册 | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||||
应用手册 | 使用逻辑器件进行设计 (Rev. C) | 1997年 6月 1日 | ||||
应用手册 | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||||
应用手册 | Live Insertion | 1996年 10月 1日 | ||||
应用手册 | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
设计和开发
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封装 | 引脚 | 下载 |
---|---|---|
PDIP (N) | 20 | 查看选项 |
SOIC (DW) | 20 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点