主页 逻辑和电压转换 触发器、锁存器和寄存器 D 型锁存器
主页
逻辑和电压转换
触发器、锁存器和寄存器
D 型锁存器

SN74ALS533A

正在供货

具有三态输出的八路 D 类透明锁存器

立即订购
数据表

SN74ALS533A

正在供货
数据表 立即订购

产品详情

Number of channels 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 75 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 28000 Features High speed (tpd 10-50ns), Inverting output Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 75 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 28000 Features High speed (tpd 10-50ns), Inverting output Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8
  • Eight Latches in a Single Package
  • 3-State Bus-Driving Inverting Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • pnp Inputs Reduce dc Loading on
    Data Lines
  • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs
  • Eight Latches in a Single Package
  • 3-State Bus-Driving Inverting Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • pnp Inputs Reduce dc Loading on
    Data Lines
  • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs

These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted outputs.

A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

The SN74ALS533A and SN74AS533A are characterized for operation from 0°C to 70°C.

 

 

These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted outputs.

A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

The SN74ALS533A and SN74AS533A are characterized for operation from 0°C to 70°C.

 

 
filter 查找其他 D 型锁存器
下载

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同，但引脚排列有所不同
SN74HCT373 正在供货 具有三态输出的八路透明 D 类锁存器 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 Octal D-Type Transparent Latches With 3-State Outputs 数据表 1994年 12月 1日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频