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Configuration Universal Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 30 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 30 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Multiplexed I/O Ports Provide Improved Bit Density
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operate With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for n-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Multiplexed I/O Ports Provide Improved Bit Density
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operate With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for n-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs, but has no effect on clearing, shifting, or storing data.

The SN54ALS299 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS299 is characterized for operation from 0°C to 70°C.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs, but has no effect on clearing, shifting, or storing data.

The SN54ALS299 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS299 is characterized for operation from 0°C to 70°C.

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* 数据表 8-Bit Universal Shift/Storage Registers With 3-State Outputs 数据表 (Rev. B) 1994年 12月 1日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
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应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Advanced Schottky (ALS and AS) Logic Families 1995年 8月 1日

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用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
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PDIP (N) 20 查看选项
SOIC (DW) 20 查看选项

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