SN74ALS166
- Synchronous Load
- Direct Overriding Clear
- Parallel-to-Serial Conversion
- Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP
The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design.
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A-H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR\ overrides all other inputs, including CLK, and sets all flip-flops to zero.
The SN74ALS166 is characterized for operation from 0°C to 70°C.
您可能感兴趣的相似产品
功能与比较器件相同且具有相同引脚
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | Parallel-Load 8-Bit Shift Register 数据表 (Rev. D) | 2000年 8月 25日 | |||
应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |||
选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
应用手册 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 | |||
用户指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
应用手册 | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||||
应用手册 | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||||
应用手册 | 使用逻辑器件进行设计 (Rev. C) | 1997年 6月 1日 | ||||
应用手册 | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||||
应用手册 | Live Insertion | 1996年 10月 1日 | ||||
应用手册 | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点