SN74ACT7813-15DL

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64 x 18 同步 FIFO 存储器 | DL | 56 | 0 to 70

等同于: SN74ACT7813-15DL.A 该器件型号与上面所列的器件型号相同。您只能订购上述器件型号的对应数量。
  • 库存:
    限制: 此限制是为了保护样片库存以支持客户设计评估阶段使用,将会在库存充裕时取消此限制。
缺货
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定价

数量 价格
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—
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质量信息

等级 Military
RoHS Yes
REACH Yes
引脚镀层/焊球材料 NiPdAu
MSL 等级/回流焊峰值温度 Level-1-260C-UNLIM
质量、可靠性
和封装信息

包含信息:

  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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更多制造信息

包含信息:

  • 制造厂地点
  • 封装厂地点
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出口管制分类

*仅供参考

  • 美国 ECCN:EAR99

更多 SN74ACT7813 信息

封装信息

封装 | 引脚 SSOP (DL) | 56
工作温度范围 (°C) 0 to 70
包装数量 | 包装 20 | TUBE

SN74ACT7813 的特性

  • Member of the Texas Instruments WidebusTM Family
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Input-Ready Flag Synchronized to Write Clock
  • Output-Ready Flag Synchronized to Read Clock
  • 64 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
  • Bidirectional Configuration and Width Expansion Without Additional Logic
  • Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 67 MHz
  • Pin-to-Pin Compatible With SN74ACT7803 and SN74ACT7805
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus and OEC are trademarks of Texas Instruments Incorporated.

SN74ACT7813 的说明

The SN74ACT7813 is a 64-word × 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

  • 库存:
    限制: 此限制是为了保护样片库存以支持客户设计评估阶段使用,将会在库存充裕时取消此限制。
缺货
Not available

定价

数量 价格
—
—
—
+

包装类型

您可以根据器件数量选择不同的包装方式,包括完整卷带、定制卷带、剪切带、管装或托盘。

定制卷带是从整盘卷带上剪下来的具有连续长度的剪切带,是一种可以对特定数量提供产品批次及生产日期跟踪的包装方式。根据行业标准,使用黄铜垫片在剪切带两端各连接一个 18 英寸的引带和尾带,以直接送入自动组装机。涉及定制卷带的 TI 订单将包含卷带费用。

剪切带是从整盘卷带上剪下来的特定长度的编带。根据所申请器件数量的不同,TI 可能会使用多条剪切带或多个盒子进行包装。

TI 通常会根据库存情况选择将管装或托盘器件以盒装或者管装或托盘形式发货。所有器件均会按照 TI 内部规定的静电放电和湿敏等级保护要求进行包装。

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可提供批次和生产日期代码选项

您可在购物车中添加器件数量以开始结算流程,并查看现有库存中可选择批次或生产日期代码的选项。

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