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SN74ACT7803

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512 x 18 同步 FIFO 存储器

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数据表

SN74ACT7803

正在供货
数据表 立即订购

产品详情

Technology family ACT Rating Military Operating temperature range (°C) 0 to 70
Technology family ACT Rating Military Operating temperature range (°C) 0 to 70
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Member of the Texas Instruments WidebusTM Family
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Input-Ready Flag Synchronized to Write Clock
  • Output-Ready Flag Synchronized to Read Clock
  • 512 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
  • Bidirectional Configuration and Width Expansion Without Additional Logic
  • Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 67 MHz
  • Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus and OEC are trademarks of Texas Instruments Incorporated.
  • Member of the Texas Instruments WidebusTM Family
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Input-Ready Flag Synchronized to Write Clock
  • Output-Ready Flag Synchronized to Read Clock
  • 512 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
  • Bidirectional Configuration and Width Expansion Without Additional Logic
  • Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 67 MHz
  • Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus and OEC are trademarks of Texas Instruments Incorporated.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.
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* 数据表 512 X 18 Clocked First-In, First-Out Memory 数据表 (Rev. C) 1998年 4月 1日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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