产品详情

Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² (15.5 mm × 10.3 mm)
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port
    and Boundary-Scan Architecture
  • Functionally Equivalent to 'F245 and 'ABT245 in the Normal-Function Mode
  • SCOPETM Instruction Set:
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline Packages (DW), Ceramic Chip Carriers(FK), and Standard Ceramic DIPs (JT)

    SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.


  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port
    and Boundary-Scan Architecture
  • Functionally Equivalent to 'F245 and 'ABT245 in the Normal-Function Mode
  • SCOPETM Instruction Set:
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline Packages (DW), Ceramic Chip Carriers(FK), and Standard Ceramic DIPs (JT)

    SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.


The 'ABT8245 scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F245 and 'ABT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The output-enable () input can be used to disable the device so that the buses are effectively isolated.

 

In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8245 is characterized for operation from -40°C to 85°C.

 

 

The 'ABT8245 scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F245 and 'ABT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The output-enable () input can be used to disable the device so that the buses are effectively isolated.

 

In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8245 is characterized for operation from -40°C to 85°C.

 

 

下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 3
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Scan Test Devices With Octal Bus Transceivers 数据表 (Rev. D) 1996-12-1
应用手册 Programming CPLDs Via the 'LVT8986 LASP 2005-11-1
EVM 用户指南 LASP Demo Board User's Guide 2005-11-1

设计与开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
支持的产品和硬件
有库存
限制:
??asset.out-of-stock-ti_zh_CN??
无货
仿真模型

BSDL Model of SN74ABT8245

SCTM006.ZIP (2 KB) - BSDL 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
SOIC (DW) 24 Ultra Librarian

订购和质量

支持和培训

视频