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D 型锁存器

SN74ABT162841

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具有三态输出的 20 位总线接口 D 类锁存器

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数据表

SN74ABT162841

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产品详情

Number of channels 20 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 89000 Features Balanced outputs, Damping resistors, Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 20 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 89000 Features Balanced outputs, Damping resistors, Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Members of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

Widebus is a trademark of Texas Instruments.
  • Members of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

Widebus is a trademark of Texas Instruments.

These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ’ABT162841 devices can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ’ABT162841 devices can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN54ABT162841, SN74ABT162841 数据表 (Rev. C) 2004年 6月 8日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
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选择指南 《高级总线接口逻辑器件选择指南》 英语版 2010年 7月 7日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
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应用手册 Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
应用手册 Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
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SSOP (DL) 56 查看选项
TSSOP (DGG) 56 查看选项
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