封装信息
| 封装 | 引脚 SOIC (D) | 8 |
| 工作温度范围 (°C) -40 to 125 |
| 包装数量 | 包装 2,500 | LARGE T&R |
SN65HVD1050A-Q1 的特性
- Qualified for Automotive Applications
- Improved Drop-In Replacement for TJA1050
- Meets or Exceeds the Requirements of ISO 11898-2
- GIFT/ICT Compliant
- ESD Protection up to ±12 kV (Human-Body Model) on Bus Pins
- High Electromagnetic Compliance (EMC)
- Bus-Fault Protection of –27 V to 40 V
- Dominant Time-Out Function
- Thermal Shutdown Protection
- Power Up and Power Down Glitch-Free Bus Inputs and Outputs
- High Input Impedance With Low VCC
- Monotonic Outputs During Power Cycling
SN65HVD1050A-Q1 的说明
The SN65HVD1050A-Q1 meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a Controller Area Network (CAN). The device is qualified for use in automotive applications.
As a CAN transceiver, this device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps). The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Designed for operation is especially harsh environments, the SN65HVD1050A-Q1 features cross-wire, overvoltage, and loss of ground protection from –27 V to 40 V, overtemperature protection, a –12-V to 12-V common-mode range, and withstands voltage transients according to ISO 7637.
Pin 8 provides for two different modes of operation: high-speed or silent mode. The high-speed mode of operation is selected by connecting S (pin 8) to ground.
If a high logic level is applied to the S pin of the SN65HVD1050A-Q1, the device enters a listen-only silent mode during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data transmission is required the local protocol controller must transition the device to high speed mode by placing a logic low on the S pin to resume full operation.
A dominant time-out circuit in the SN65HVD1050A-Q1 prevents the driver from blocking network communication with a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD.
VREF (pin 5) is available as a VCC / 2 voltage reference.