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SN54HC195

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4 位并行访问移位寄存器

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SN54HC195

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Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² (— mm × — mm)
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 4-Bit Parallel-Access Shift Registers 数据表 (Rev. A) 2007-11-16
* SMD SN54HC195 SMD 5962-86827 2016-6-21

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