SN54ACT3632
- Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
- Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions
- Mailbox-Bypass Register for Each FIFO
- Programmable Almost-Full and Almost-Empty Flags
- Microprocessor Interface Control Logic
- IRA, ORA, AEA\, and AFA\ Flags Synchronized by CLKA
- Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA
- IRB, ORB, AEB\, and AFB\ Flags Synchronized by CLKB
- Low-Power 0.8-um Advanced CMOS Technology
- Supports Clock Frequencies up to 50 MHz
- Fast Access Times of 13 ns
- Packaged in 132-Pin Ceramic Quad Flat Package
The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.
The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA\, AFB\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA\, AEB\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN54ACT3632 is characterized for operation over the full military temperature range of -55°C to 125°C.
For more information on this device family, see the following application reports:
- FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007) - Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)
- Metastability Performance of Clocked FIFOs (literature number SCZA004)
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | 512 X 36 X 2 Clocked Bidirectional First-In, First-Out 数据表 (Rev. A) | 1998年 4月 1日 | |||
应用手册 | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||||
选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
应用手册 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 | |||
用户指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
应用手册 | 选择正确的电平转换解决方案 (Rev. A) | 英语版 (Rev.A) | 2006年 3月 23日 | |||
应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
应用手册 | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||||
应用手册 | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997年 6月 1日 | ||||
应用手册 | 使用逻辑器件进行设计 (Rev. C) | 1997年 6月 1日 | ||||
应用手册 | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996年 4月 1日 |
设计和开发
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订购和质量
- RoHS
- REACH
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- MSL 等级/回流焊峰值温度
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