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PCI2050B

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PCI2050B

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产品详情

Type Bridge Protocols PCIe Applications PCIe Number of channels 2 Speed (max) (Gbps) 0.066 Supply voltage (V) 3.3, 5 Rating Catalog Operating temperature range (°C) -40 to 85
Type Bridge Protocols PCIe Applications PCIe Number of channels 2 Speed (max) (Gbps) 0.066 Supply voltage (V) 3.3, 5 Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PDV) 208 784 mm² 28 x 28 NFBGA (ZWT) 257 256 mm² 16 x 16
  • Two 32-bit, 66-MHz PCI buses
  • 3.3-V core logic with universal PCI interfaces compatible
    with 3.3-V and 5-V PCI signaling environments
  • Internal two-tier arbitration for up to nine secondary
    bus masters and supports an external secondary bus arbiter
  • Ten secondary PCI clock outputs
  • Independent read and write buffers for each direction
  • Burst data transfers with pipeline architecture to maximize
    data throughput in both directions
  • Supports write combing for enhanced data throughput
  • Up to three delayed transactions in both directions
  • Supports the frame-to-frame delay of only four PCI clocks
    from one bus to another
  • Bus locking propagation
  • Predictable latency per PCI Local Bus Specification
  • Architecture configurable for PCI Bus Power Management
    Interface Specification
  • CompactPCI hot-swap functionality
  • Secondary bus is driven low during reset
  • VGA/palette memory and I/O decoding options
  • Advanced submicron, low-power CMOS technology
  • 208-terminal PDV, 208-terminal PPM, or 257-terminal
    MicroStar BGA™ package
  • Two 32-bit, 66-MHz PCI buses
  • 3.3-V core logic with universal PCI interfaces compatible
    with 3.3-V and 5-V PCI signaling environments
  • Internal two-tier arbitration for up to nine secondary
    bus masters and supports an external secondary bus arbiter
  • Ten secondary PCI clock outputs
  • Independent read and write buffers for each direction
  • Burst data transfers with pipeline architecture to maximize
    data throughput in both directions
  • Supports write combing for enhanced data throughput
  • Up to three delayed transactions in both directions
  • Supports the frame-to-frame delay of only four PCI clocks
    from one bus to another
  • Bus locking propagation
  • Predictable latency per PCI Local Bus Specification
  • Architecture configurable for PCI Bus Power Management
    Interface Specification
  • CompactPCI hot-swap functionality
  • Secondary bus is driven low during reset
  • VGA/palette memory and I/O decoding options
  • Advanced submicron, low-power CMOS technology
  • 208-terminal PDV, 208-terminal PPM, or 257-terminal
    MicroStar BGA™ package

The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.

The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 PCI-to-PCI Bridge, PCI2050B 数据表 (Rev. G) 2013年 4月 15日
* 勘误表 PCI2050B Errata (Rev. B) 2009年 4月 9日
* 用户指南 HSSC MicroStar BGA Discontinued and Redesigned 2022年 5月 8日
应用手册 Comparing the PCI2050B to the PCI2050 2006年 2月 3日
应用手册 Difference Between the Intel 21150ac/bc and the PCI2050/2050B (Rev. B) 2005年 11月 15日

设计和开发

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仿真模型

PCI2050B IBIS Model

SLLM076.ZIP (15 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
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LQFP (PDV) 208 查看选项
NFBGA (ZWT) 257 查看选项
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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
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