返回页首

产品详细信息

参数

Function Serializer Color depth (bpp) 18 Pixel clock min (MHz) 3 Pixel clock (Max) (MHz) 40 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Capable to Drive Shielded Twisted-Pair Cable, Embedded Clock CDR, LOCK Output Flag, All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications, User Selectable Clock Edge for Parallel Data Signal conditioning Fixed Pre-Emphasis EMI reduction Progressive Turn On (PTO), LVDS Outputs Diagnostics Total throughput (Mbps) 960 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new 查找其它 显示 SerDes

封装|引脚|尺寸

TQFP (PFB) 48 81 mm² 9 x 9 WQFN (NJU) 48 49 mm² 7 x 7 open-in-new 查找其它 显示 SerDes

特性

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range 0°C to +70°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

open-in-new 查找其它 显示 SerDes

描述

The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

open-in-new 查找其它 显示 SerDes
下载

技术文档

= 特色
未找到结果。请清除搜索,并重试。 查看所有 4
类型 标题 下载最新的英文版本 发布
* 数据表 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer 数据表 2013年 4月 16日
用户指南 SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Guide 2012年 1月 25日
应用手册 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (cn) 下载最新的英文版本 (Rev.A) 2008年 9月 4日
应用手册 App Note 1826 Extending Reach of a FPD-Link II Intrfce w/Cable Drvrs & Equalzr 下载最新的英文版本 (Rev.A) 2008年 3月 24日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

设计工具和仿真

仿真工具 下载
document-generic 用户指南 document-generic 下载英文版本 (Rev.A)

CAD/CAE 符号

封装 引脚 下载
TQFP (PFB) 48 视图选项
WQFN (NJU) 48 视图选项

订购与质量

支持与培训

可获得 TI E2E™ 论坛的工程师技术支持

所有内容均由 TI 和社区网友按“原样”提供,并不构成 TI 规范。参阅使用条款

如果您对质量、包装或订购 TI 产品有疑问,请参阅 TI 支持