DS90LV049Q-Q1
- AECQ-100 Grade 1
- Up to 400 Mbps Switching Rates
- Flow-Through Pinout Simplifies PCB Layout
- 50 ps Typical Driver Channel-to-Channel Skew
- 50 ps Typical Receiver Channel-to-Channel Skew
- 3.3 V Single Power Supply Design
- TRI-STATE Output Control
- Internal Fail-Safe Biasing of Receiver Inputs
- Low Power Dissipation (70 mW at 3.3 V Static)
- High Impedance on LVDS Outputs on Power Down
- Conforms to TIA/EIA-644-A LVDS Standard
- Available in Low Profile 16 Pin TSSOP Package
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The DS90LV049Q is a dual CMOS flow-through differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV049Q drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3 V CMOS signals. The LVDS input buffers have internal failsafe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049Q supports a TRI-STATE function for a low idle power state when the device is not in use.
The EN and EN inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.
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技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair 数据表 (Rev. D) | 2013年 4月 16日 | |||
应用简报 | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||||
应用手册 | An Overview of LVDS Technology | 1998年 10月 5日 |
设计和开发
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封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
TSSOP (PW) | 16 | Ultra Librarian |
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