DS25BR100
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Receive Equalization Reduces ISI Jitter Due to Media Loss
- Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
- On-Chip 100Ω Input and Output Termination:
- Minimizes Insertion and Return Losses
- Reduces Component Count
- Minimizes Board Space
- DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm WSON-8 Space Saving Package
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The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.
技术文档
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha & Rcve Equalization 数据表 (Rev. F) | 2013年 4月 14日 | |||
| 应用手册 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013年 4月 29日 | ||||
| 应用手册 | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013年 4月 26日 | ||||
| 设计指南 | 适用于 Xilinx FPGA 的模拟器件 解决方案指南 | 2012年 4月 24日 | ||||
| 用户指南 | SMA to RJ45 Adapter Board User Guide | 2012年 1月 26日 | ||||
| 用户指南 | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012年 1月 25日 | ||||
| 应用手册 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (cn) | 最新英语版本 (Rev.A) | 2008年 9月 4日 |
设计和开发
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DS25BR100EVK — 具有发送预强调和接收均衡功能的 3.125 Gbps LVDS 单通道缓冲器系列
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
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