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DP83815

不推荐用于新设计

10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter)

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数据表

DP83815

不推荐用于新设计
数据表 立即订购

产品详情

Datarate (Mbps) 10/100 Interface type PCI (33MHz) Number of ports Single Rating Catalog Features 5-V tolerant I/Os Supply voltage (V) 3.3 Operating temperature range (°C) 0 to 70
Datarate (Mbps) 10/100 Interface type PCI (33MHz) Number of ports Single Rating Catalog Features 5-V tolerant I/Os Supply voltage (V) 3.3 Operating temperature range (°C) 0 to 70
LQFP (PGE) 144 484 mm² 22 x 22 NFBGA (NZG) 160 225 mm² 15 x 15
  • IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
  • Bus master - burst sizes of up to 128 dwords (512 bytes)
  • BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
  • Wake on LAN (WOL) support compliant with PC98, PC99, SecureOn, and OnNow, including directed packets, Magic Packet?, VLAN packets, ARP packets, pattern match packets, and Phy status change
  • Clkrun function for PCI Mobile Design Guide
  • Virtual LAN (VLAN) and long frame support
  • Support for IEEE 802.3x Full duplex flow control
  • Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
  • Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management
  • Internal 2 KB Transmit and 2 KB Receive data FIFOs
  • Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
  • Flash/PROM interface for remote boot support
  • Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
  • IEEE 802.3 10BASE-T transceiver with integrated filters
  • IEEE 802.3u 100BASE-TX transceiver
  • Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
  • IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
  • Full Duplex support for 10 and 100 Mb/s data rates
  • Single 25 MHz reference clock
  • 144-pin LQFP and 160-pin LBGA packages
  • Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
  • IEEE 802.3u MII for connecting alternative external Physical Layer Devices
  • IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
  • Bus master - burst sizes of up to 128 dwords (512 bytes)
  • BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
  • Wake on LAN (WOL) support compliant with PC98, PC99, SecureOn, and OnNow, including directed packets, Magic Packet?, VLAN packets, ARP packets, pattern match packets, and Phy status change
  • Clkrun function for PCI Mobile Design Guide
  • Virtual LAN (VLAN) and long frame support
  • Support for IEEE 802.3x Full duplex flow control
  • Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
  • Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management
  • Internal 2 KB Transmit and 2 KB Receive data FIFOs
  • Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
  • Flash/PROM interface for remote boot support
  • Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
  • IEEE 802.3 10BASE-T transceiver with integrated filters
  • IEEE 802.3u 100BASE-TX transceiver
  • Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
  • IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
  • Full Duplex support for 10 and 100 Mb/s data rates
  • Single 25 MHz reference clock
  • 144-pin LQFP and 160-pin LBGA packages
  • Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
  • IEEE 802.3u MII for connecting alternative external Physical Layer Devices

DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.

The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.

The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.
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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 10/100Mb/s Integrated PCI Ethernet Media Access Cntr & Physical Layer MacPhyter 数据表 (Rev. E) 2011年 8月 31日
更多文献资料 AN-1351 MAC Address Prog for DP83816 MacPHYTER-II and DP83815 MacPHYTER 下载英文版本 2005年 1月 5日
更多文献资料 AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II (cn) 下载英文版本 2004年 5月 1日
更多文献资料 AN-1287 DP83815 MacPHYTER & DP83816 MacPHYTER-II High Data Rate Stress Testing 下载英文版本 2004年 5月 1日

设计和开发

如需其他信息或资源，请查看下方列表，点击标题即可进入详情页面。

驱动程序或库

DP83815-6MACPHYTER-SW — DP83816“MacPHYTER II”软件驱动程序和实用程序

Ethernet drivers for the DP83816 and DP83815 MAC+PHY devices
下载
驱动程序或库

ETHERNET-SW — 以太网 PHY Linux 驱动器和工具

德州仪器 (TI) 以太网物理层收发器 (PHY) Linux 驱动程序支持通过串行管理接口 (MDC/MDIO) 进行通信，以配置和读取 PHY 寄存器。

此 USB-2-MDIO 软件在调试和原型设计期间可实现直接寄存器访问。  此工具支持所有 TI 以太网 PHY。

启用驱动程序支持

使用“make menuconfig”（也可以使用“make xconfig”或“make nconfig”）配置内核

Menuconfig 位置

//更改以下示例中的符号字段以匹配部件号
符号：DP83848_PHY [=y]
类型：tristate
提示：德州仪器 (TI) DP83848 PHY 驱动程序
  位置：
(...)

用户指南: PDF
了解详情
驱动程序或库

DP83816 'MacPHYTER II' Software Drivers & Utilities

SLLC425.ZIP (1285 KB)
下载
仿真模型

DP83815 IBIS Model

SNLM001.ZIP (54 KB) - IBIS Model
下载
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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模拟工具

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表 

需要 HSpice (...)

用户指南: PDF
下载英文版本 (Rev.A): PDF
了解详情
封装 引脚数 下载
LQFP (PGE) 144 了解详情
NFBGA (NZG) 160 了解详情

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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