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CY74FCT257T

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具有三态输出的四路 2 选 1 数据选择器/多路复用器

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CY74FCT257T

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Technology family FCT Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
Technology family FCT Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DBQ) 16 29.4 mm² (4.9 mm × 6 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOIC (DW) 16 106.09 mm² (10.3 mm × 10.3 mm)
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • 3-State Outputs

The CY74FCT257T has four identical two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The I0 inputs are selected when S is low, and the I1 inputs are selected when S is high. Data at the output is noninverted.

The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in the high-impedance state when the output-enable (OE\) input is high.

All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tied together. OE\ inputs must ensure that there is no overlap when outputs of 3-state devices are tied together.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT257T has four identical two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The I0 inputs are selected when S is low, and the I1 inputs are selected when S is high. Data at the output is noninverted.

The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in the high-impedance state when the output-enable (OE\) input is high.

All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tied together. OE\ inputs must ensure that there is no overlap when outputs of 3-state devices are tied together.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Quad 2-Input Multiplexer With 3-State Outputs 数据表 (Rev. D) 2001-11-2
* 用户指南 CYFCT Parameter Measurement Information 2001-4-2

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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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SSOP (DBQ) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOIC (DW) 16 Ultra Librarian
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