封装信息
| 封装 | 引脚 QFP (PGB) | 44 |
| 工作温度范围 (°C) 0 to 70 |
| 包装数量 | 包装 96 | JEDEC TRAY (10+1) |
CLC021 的特性
- SMPTE 259M Serial Digital Video Standard Compliant
- Supports All NTSC and PAL Standard Component and Composite Serial Video Data Rates
- No External Serial Data Rate Setting or VCO Filtering Components Required
- Fast VCO Lock Time: <75 µs at 270 Mbps
- Built-In Self-Test (BIST) and Video Test Pattern Generator (TPG) with 16 Internal Patterns
- Automatic EDH Character and Flag Generation and Insertion per SMPTE RP 165
- Non-SMPTE Mode Operation as Parallel-to-Serial Converter
- NRZ-to-NRZI Conversion Control
- HCMOS/LSTTL‐Compatible Data and Control Inputs and Outputs for CLC021AVGZ‐5.0, LVCMOS for CLC021AVGZ‐3.3
- 75Ω ECL-Compatible, Differential, Serial Cable-Driver Outputs
- Single Power Supply Operation: 5V (CLC021AVGZ‐5.0) or 3.3V (CLC021AVGZ‐3.3) in TTL or ECL Systems
- Low Power: Typically 235 mW
- JEDEC 44-Lead Metric PQFP Package
- Commercial Temperature Range 0°C to +70°C
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CLC021 的说明
The CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital data conforming to SMPTE 125M and 267M component video and SMPTE 244M composite video standards. The CLC021 can also serialize other 8- or 10-bit parallel data. The CLC021 operates at data rates from below 100 Mbps to over 400 Mbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components*.
Functions performed by the CLC021 include: parallel-to-serial data conversion, ITU-R BT.601-4 input data clipping, data encoding using the SMPTE polynomial (X9+X4+1), data format conversion from NRZ to NRZI, parallel data clock frequency multiplication and encoding with the serial data, and differential, serial output data driving. The CLC021 has circuitry for automatic EDH character and flag generation and insertion per SMPTE RP-165. The CLC021 has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with 16 component video test patterns: reference black, PLL and EQ pathologicals and modified colour bars in 4:3 and 16:9 raster formats for NTSC and PAL formats*.
The CLC021 has inputs for enabling sync detection, non-SMPTE mode operation, enabling the EDH function, NRZ/NRZI mode control and an external reset control. Outputs are provided for H, V and F bits, new TRS sync character position indication, ancilliary data header detection, NTSC/PAL raster indication and PLL lock detect. Separate power pins for the output driver, VCO and the serializer improve power supply rejection, output jitter and noise performance.
The CLC021AVGZ-5.0V is powered by a single +5V supply. The CLC021AVGZ-3.3V is powered by a single +3.3V supply. Power dissipation is typically 235 mW including two 75Ω back-matched output loads. The device is packaged in a JEDEC metric 44-lead PQFP.