高性能、低相位噪声、低偏移的时钟同步器（使参考时钟与 VCXO 同步）
产品详细信息
参数
封装|引脚|尺寸
特性
- High Performance LVPECL and LVCMOS PLL Clock Synchronizer
- Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
- Accepts LVCMOS Input Frequencies up to 200 MHz
- VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
- VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
- Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
- Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
- Efficient Jitter Cleaning From Low PLL Loop Bandwidth
- Low Phase Noise PLL Core
- Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
- Wide Charge Pump Current Range From
200 µA to 3 mA - Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
- Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
- Analog and Digital PLL Lock Indication
- Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
- Frequency Hold-Over Mode Improves Fail-Safe Operation
- Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
- SPI Controllable Device Setting
- 3.3-V Power Supply
- Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
- Industrial Temperature Range –40°C to 85°C
All trademarks are the property of their respective owners.
描述
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O
VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.
The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.
All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.
The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.
技术文档
设计与开发
有关其他条款或所需资源，请点击下面的任何链接来查看详情页面。硬件开发
说明
The ADS5474EVM is a circuit board which allows the designer to run an evaluation of Texas Instruments ADS5474 device, a 14-bit 400 MSPS ADC. With the supplied Logic analyzer breakout board, the ADC LVDS output can be directly captured using either an Agilent E5405A or Tektronix P6980 touchless (...)
特性
- Transformer coupled analog input path
- Texas Instrument’s THS9001 analog input path
- LVDS capture ability
说明
ADS5483EVM 是能让设计者评估德州仪器 (TI) ADS5483 器件（具有 DDR LVDS 输出的 16 位 135 MSPS ADC）的电路板。借助提供的逻辑分析器输出板，可以使用 Agilent E5405A 或 Tektronix P6980 非接触式探针直接采集 ADC LVDS 输出。ADS5483EVM 还与 TI 的 TSW1200EVM 高速 LVDS 评估和采集系统兼容，允许采集样片并将其传递到 PC，以进行快速分析和评估。
ADS5483EVM 还包括德州仪器 (TI) 的新款 10 路输出低抖动时钟同步器和抖动消除器器件 - CDCE72010，它可用于将时钟输入驱使到 ADS5483 中。我们为外部 VCXO 和晶体带通滤波器提供了开放套接，允许对组合的高性能 ADC 与时钟电路（相当于最终的系统级解决方案）进行快速评估。此外，还为 EVM 提供了外部时钟源，后者可通过 CDCE72010 进行路由或直接传递到 ADS5483 时钟输入。
特性
- 变压器耦合模拟输入路径
- CDCE72010 抖动时钟同步器和抖动消除器时钟电路
- DDR LVDS 输出和采集能力
说明
The CDC7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.
The PLL loop bandwidth and damping factor can be adjusted to meet (...)
特性
- Operates up to 800 MHz
- Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
- Can be used as a simple 1:5 LVPECL buffer with output dividing options
- Differential outputs programmable by serial peripheral interface (SPI)
说明
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.
The PLL loop bandwidth and damping factor can be adjusted to meet (...)
特性
- Output frequency up to 1500 MHz
- Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
- Can be used as a simple 1:5 LVPECL buffer with output dividing options
- Differential outputs programmable by serial peripheral interface (SPI)
说明
TheCDCM7005QFN-EVM is an evaluation module designed to aid in evaluating the performance of the CDCM7005, which is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates (...)
特性
- Output frequency up to 1500 MHz
- Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
- Can be used as a simple 1:5 LVPECL buffer with output dividing options
- Differential outputs programmable by serial peripheral interface (SPI)
说明
DAC5688EVM 是一块电路板，它允许设计人员评估具有宽带 LVDS 数据输入、集成 2x/4x/8x 内插滤波器、32 位 NCO 和内部参考电压的德州仪器 (TI) 双通道 16 位 800MSPS 数模转换器 (DAC)。EVM 提供了可在各种时钟、输入条件下测试 DAC5688 的灵活环境。
它能与 TSW3100 配合使用以执行各种测试程序。TSW3100 生成了测试模式，该模式将通过单行速度可达 250MSPS 的双路 CMOS 端口被馈送至 DAC5688。DAC5688EVM 具有可使 TSW3100 板与 DAC5688 同步的可编程时钟芯片。
特性
- DAC5688 的综合测试能力
- 与 TSW3100 信号发生器 EVM 直接连接
- 具有能与 VCXO 或外部时钟源配合使用的可编程低抖动时钟合成器
- 与 TSW3100 保持时钟同步，以确保信号完整性
- 具有完整功能 GUI 的软件支持，以确保轻松测试
设计工具和仿真
借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中，您可以搜索 TI 器件、了解产品系列、打开测试台并对您的设计进行仿真，从而进一步分析选定的器件。您还可对多个 TI 器件进行联合仿真，以更好地展现您的系统。
除了一个完整的预加载模型库之外，您还可以在 PSPICE-FOR-TI 工具中轻松访问 TI 器件的全新技术资料。在您确认找到适合您应用的器件后，可访问 TI store 购买产品。
借助 PSpice for TI，您可使用合适的工具来满足您在整个设计周期（从电路探索到设计开发和验证）的仿真需求。免费获取、轻松入门。立即下载 PSpice 设计和仿真套件，开始您的设计。
入门
- 申请使用 PSPICE-FOR-TI 仿真器
- 下载并安装
- 观看有关仿真入门的培训
特性
- 利用 Cadence PSpice 技术
- 带有一套数字模型的预装库可在最坏情形下进行时序分析
- 动态更新确保您可以使用全新的器件型号
- 针对仿真速度进行了优化，且不会降低精度
- 支持对多个产品进行同步分析
- 基于 OrCAD Capture 框架，提供对业界广泛使用的原理图捕获和仿真环境的访问权限
- 可离线使用
- 在各种工作条件和器件容许范围内验证设计，包括
- 自动测量和后处理
- Monte Carlo 分析
- 最坏情形分析
- 热分析
特性
The lab view based tool can:
- Determine the PFD frequency automatically
- Calculate loop bandwidth, Phase margin and Jitter peaking
- Predict the PLL output Phase noise
- Calculate Phase Jitter (rms)
参考设计
设计文件
-
download TIDA-01187 BOM.pdf (54KB) -
download TIDA-01187 Assembly Drawing.pdf (48KB) -
download TIDA-01187 PCB.pdf (212KB) -
download TIDA-01187 CAD Files.zip (303KB) -
download TIDA-01187 Gerber.zip (105KB)
设计文件
-
download TIDA-00075 BOM.pdf (57KB) -
download TIDA-00075 Layer Plots.zip (3997KB)
CAD/CAE 符号
| 封装 | 引脚 | 下载 |
|---|---|---|
| BGA (ZVA) | 64 | 了解详情 |
| VQFN (RGZ) | 48 | 了解详情 |
订购与质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/FIT 估算
- 材料成分
- 认证摘要
- 持续可靠性监测
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