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CDC111

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3.3V LVPECL 差分时钟驱动器

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CDC111

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产品详情

Function Differential Output frequency (max) (MHz) 500 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) 0 to 70 Rating Catalog Output type LVPECL Input type LVPECL
Function Differential Output frequency (max) (MHz) 500 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) 0 to 70 Rating Catalog Output type LVPECL Input type LVPECL
PLCC (FN) 28 155.0025 mm² 12.45 x 12.45
  • Low-Output Skew for Clock-Distribution Applications
  • Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
  • Distributes Differential Clock Inputs to Nine Differential Clock Outputs
  • Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
  • Single-Ended LVPECL-Compatible Output Enable
  • Packaged in Plastic Chip Carrier
  • Low-Output Skew for Clock-Distribution Applications
  • Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
  • Distributes Differential Clock Inputs to Nine Differential Clock Outputs
  • Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
  • Single-Ended LVPECL-Compatible Output Enable
  • Packaged in Plastic Chip Carrier

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).

The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C.

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).

The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 1-Line To 9-Line Differential LVPECL Clock Driver 数据表 (Rev. G) 1999年 8月 28日
应用手册 AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 2007年 10月 17日
应用手册 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 2003年 2月 19日

设计和开发

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仿真模型

CDC111 IBIS Model

SCAC030.ZIP (6 KB) - IBIS Model
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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