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PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Operating Frequency Range
    • Up to 18MHz (Typ) at VCC = 5V
    • Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Three Phase Comparators
    • EXCLUSIVE-OR
    • Edge-Triggered JK Flip-Flop
    • Edge-Triggered RS Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Operating Power Supply Voltage Range
    • VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
    • Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control
  • Operating Frequency Range
    • Up to 18MHz (Typ) at VCC = 5V
    • Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Three Phase Comparators
    • EXCLUSIVE-OR
    • Edge-Triggered JK Flip-Flop
    • Edge-Triggered RS Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Operating Power Supply Voltage Range
    • VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
    • Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

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类型 标题 下载最新的英语版本 日期
* 数据表 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A 数据表 (Rev. J) 2003年 11月 21日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日
应用手册 Implementation of FSK Modulation and Demodulation using CD74HC4046A 2013年 11月 25日
应用手册 Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 2008年 3月 31日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
应用手册 CMOS Phase-Locked-Loop Applications (Rev. B) 2002年 9月 19日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
应用手册 Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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PDIP (N) 16 查看选项
SOIC (D) 16 查看选项
SOP (NS) 16 查看选项
TSSOP (PW) 16 查看选项

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  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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