产品详情

Number of channels 2 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) -24 IOH (max) (mA) 24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) -24 IOH (max) (mA) 24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Inputs Are TTL-Voltage Compatible
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

  • Inputs Are TTL-Voltage Compatible
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

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类型 标题 下载最新的英语版本 日期
* 数据表 CD54ACT112, CD74ACT112 数据表 2003年 1月 17日
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选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
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应用手册 Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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  • MSL 等级/回流焊峰值温度
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