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CD4724B-MIL

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CMOS 8 位可寻址锁存器

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CD4724B-MIL

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产品详情

Function Addressable Latch Number of channels 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Data rate (max) (Mbps) 16 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Function Addressable Latch Number of channels 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Data rate (max) (Mbps) 16 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Serial data input
  • Active parallel output
  • Storage register capability
  • Master clear
  • Can function as demultiplexer
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Multi-line decoders
    • A/D converters

NOT RECOMMENDED FOR NEW DESIGNS SEE CD4099B
  • Serial data input
  • Active parallel output
  • Storage register capability
  • Master clear
  • Can function as demultiplexer
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Multi-line decoders
    • A/D converters

NOT RECOMMENDED FOR NEW DESIGNS SEE CD4099B

CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.

The CD4724B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.

The CD4724B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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类型 标题 下载最新的英语版本 日期
* 数据表 CD4724B TYPES 数据表 (Rev. C) 2003年 6月 27日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
应用手册 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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