主页 逻辑和电压转换 触发器、锁存器和寄存器 移位寄存器
主页
逻辑和电压转换
触发器、锁存器和寄存器
移位寄存器

CD4034B-MIL

正在供货

CMOS 8 级静态双向并行/串行输入/输出总线寄存器

立即订购
数据表

CD4034B-MIL

正在供货
数据表 立即订购

产品详情

Configuration Universal Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 24 425.45 mm² 31.75 x 13.4
  • Bidirectional parallel data input
  • Parallel or serial inputs/parallel outputs
  • Asynchronous or synchronous parallel data loading
  • Parallel data-input enable on "A" data lines (3-state output)
  • Data recirculation for register expansion
  • Multipackage register expansion
  • Fully static operation dc-to-10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register
    • Shift right/shift left register
    • Shift right/shift left with parallel loading
    • Address register
    • Buffer register
    • Bus system register with enable parallel lines at bus side
    • Double bus register system
    • Up-Down Johnson or ring counter
    • Pseudo-random code generators
    • Sample and hold register (storage, counting, display)
    • Frequency and phase comparator
  • Bidirectional parallel data input
  • Parallel or serial inputs/parallel outputs
  • Asynchronous or synchronous parallel data loading
  • Parallel data-input enable on "A" data lines (3-state output)
  • Data recirculation for register expansion
  • Multipackage register expansion
  • Fully static operation dc-to-10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register
    • Shift right/shift left register
    • Shift right/shift left with parallel loading
    • Address register
    • Buffer register
    • Bus system register with enable parallel lines at bus side
    • Double bus register system
    • Up-Down Johnson or ring counter
    • Pseudo-random code generators
    • Sample and hold register (storage, counting, display)
    • Frequency and phase comparator

CD4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to:

1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).

Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided.

All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering.

Register expansion can be accomplished by simply cascading CD4034B packages.

The CD4034B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to:

1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).

Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided.

All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering.

Register expansion can be accomplished by simply cascading CD4034B packages.

The CD4034B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).
open-in-new 查找其他 移位寄存器
下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 9
类型 标题 下载最新的英语版本 日期
* 数据表 CD4034B TYPES 数据表 (Rev. B) 2003年 6月 16日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
应用手册 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 下载
CDIP (J) 24 查看选项
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频