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参数

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Bits (#) 7 Voltage (Nom) (V) 5, 10, 15 F @ nom voltage (Max) (MHz) 8 ICC @ nom voltage (Max) (mA) 0.03 tpd @ nom Voltage (Max) (ns) 720 IOL (Max) (mA) 1.5 IOH (Max) (mA) -1.5 Function Counter Type Decade Rating Catalog Operating temperature range (C) -55 to 125 open-in-new 查找其它 计数器/算术/奇偶校验功能 IC

封装|引脚|尺寸

PDIP (N) 16 181 mm² 19.3 x 9.4 open-in-new 查找其它 计数器/算术/奇偶校验功能 IC

特性

  • Separate clock-up and clock-down lines
  • Capable of driving common cathode LEDs and other displays directly
  • Allows cascading without any external circuitry
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 V at VDD = 15 V
  • 5 V, 10 V and 15 V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices".
  • Applications
    • Rate comparators
    • General counting applications where display is desired
    • Up-down counting applications where input pulses are random in nature
open-in-new 查找其它 计数器/算术/奇偶校验功能 IC

描述

CD40110B is a dual-clocked up/down counter with a special preconditioning circuit that allows the counter to be clocked, via positive going inputs, up or down regardless of the state or timing (within 100 ns typ.) of the other clock line.

The clock signal is fed into the control logic and Johnson counter after it is preconditioned. The outputs of the Johnson counter (which include anti-lock gating to avoid being locked at an illegal state) are fed into a latch. This data can be fed directly to the decoder through the latch or can be strobed to hold a particular count while the Johnson counter continues to be clocked. The decoder feeds a seven-segment bipolar output driver which can source up to 25 mA to drive LEDs and other displays such as low-voltage fluorescent and incandescent lamps.

A short durating negative-going pulse appears on the BORROW output when the count changes from 0 to 9 or the CARRY output when the count changes from 9 to 0. At the other times the BORROW and CARRY outputs are a logic 1.

The CARRY and BORROW outputs can be tied directly to the clock-up and clock-down lines respectively of another CD40110B for easy cascading of several counters.

The CD40110B types are supplied in 16-0lead dual-in-line ceramic packages (D and F suffixes), and 16-lead dual-in-line plastic package (E suffix), and also available in chip form, (H suffix).

open-in-new 查找其它 计数器/算术/奇偶校验功能 IC
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技术文档

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类型 标题 下载最新的英文版本 发布
* 数据表 CMOS Decade Up-Down Counter/Latch/Display Driver 数据表 1998年 11月 21日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日
选择指南 逻辑器件指南 2009 (Rev. Z) 下载最新的英文版本 (Rev.AB) 2010年 7月 7日
解决方案指南 LOGIC Pocket Data Book 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book 2003年 11月 14日
更多文献资料 Logic Cross-Reference 2003年 10月 7日
应用手册 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

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document-generic 用户指南
$10.00
说明
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
特性
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE 符号

封装 引脚 下载
PDIP (N) 16 视图选项

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