产品详情

Sample rate (max) (Msps) 40 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 100 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 600 Architecture Pipeline SNR (dB) 84 ENOB (bit) 11.1 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 40 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 100 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 600 Architecture Pipeline SNR (dB) 84 ENOB (bit) 11.1 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
TQFP (PAG) 64 144 mm² 12 x 12
  • Binary or 2’s Complement Output Format
  • Single Supply Operation
  • Internal Sample-and-Hold
  • Outputs 2.4V to 5V Compatible
  • Power Down Mode
  • Pin-Compatible with ADC12DL066
  • Internal/External Reference

Key Specifications

  • SNR (fIN = 10 MHz): 68 dB (typ)
  • ENOB (fIN = 10 MHz): 10.9 bits (typ)
  • SFDR (fIN = 10 MHz): 80 dB (typ)
  • Data Latency: 6 Clock Cycles
  • Supply Voltage: +5V ±5%
  • Power Consumption, Operating
    • (Operating): 600 mW (typ)
    • (Power Down Mode): 75 mW (typ)

All trademarks are the property of their respective owners.

  • Binary or 2’s Complement Output Format
  • Single Supply Operation
  • Internal Sample-and-Hold
  • Outputs 2.4V to 5V Compatible
  • Power Down Mode
  • Pin-Compatible with ADC12DL066
  • Internal/External Reference

Key Specifications

  • SNR (fIN = 10 MHz): 68 dB (typ)
  • ENOB (fIN = 10 MHz): 10.9 bits (typ)
  • SFDR (fIN = 10 MHz): 80 dB (typ)
  • Data Latency: 6 Clock Cycles
  • Supply Voltage: +5V ±5%
  • Power Consumption, Operating
    • (Operating): 600 mW (typ)
    • (Power Down Mode): 75 mW (typ)

All trademarks are the property of their respective owners.

The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (Msps), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 mW at 40 Msps, including the reference current. The Power Down feature reduces power consumption to 75 mW.

The differential inputs provide a full scale differential input swing equal to 2VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs for the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2’s complement.

For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage, making the outputs compatible with low voltage systems. The ADC12D040’s speed, resolution and single supply operation make it well suited for a variety of applications.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to facilitate the product evaluation process

The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (Msps), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 mW at 40 Msps, including the reference current. The Power Down feature reduces power consumption to 75 mW.

The differential inputs provide a full scale differential input swing equal to 2VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs for the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2’s complement.

For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage, making the outputs compatible with low voltage systems. The ADC12D040’s speed, resolution and single supply operation make it well suited for a variety of applications.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to facilitate the product evaluation process

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类型 标题 下载最新的英语版本 日期
* 数据表 ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter w/ Internal/Extrnal Ref 数据表 (Rev. E) 2013年 3月 4日
EVM 用户指南 Evaluation Board User's Guide A/D Converters with Internal Ref and Sample & Hold (Rev. A) 2014年 8月 11日

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TQFP (PAG) 64 了解详情

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