产品详情

Sample rate (max) (Msps) 105 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 400 Architecture Pipeline SNR (dB) 71 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 105 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 400 Architecture Pipeline SNR (dB) 71 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (RTV) 32 25 mm² 5 x 5
  • 1 GHz Full Power Bandwidth
  • Internal Reference and Sample-and-Hold Circuit
  • Low Power Consumption
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Single +3.0V or +3.3V Supply Operation
  • Power-Down Mode
  • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 105 MSPS
  • SNR: (fIN = 240 MHz) 69 dBFS (typ)
  • SFDR: (fIN = 240 MHz) 82 dBFS (typ)
  • Full Power Bandwidth: 1 GHz (typ)
  • Power Consumption:
    • 350 mW (typ), VA=3.0 V
    • 400 mW (typ), VA=3.3 V

All trademarks are the property of their respective owners.

  • 1 GHz Full Power Bandwidth
  • Internal Reference and Sample-and-Hold Circuit
  • Low Power Consumption
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Single +3.0V or +3.3V Supply Operation
  • Power-Down Mode
  • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 105 MSPS
  • SNR: (fIN = 240 MHz) 69 dBFS (typ)
  • SFDR: (fIN = 240 MHz) 82 dBFS (typ)
  • Full Power Bandwidth: 1 GHz (typ)
  • Power Consumption:
    • 350 mW (typ), VA=3.0 V
    • 400 mW (typ), VA=3.3 V

All trademarks are the property of their respective owners.

The ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power.

A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12C105 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

The ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power.

A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12C105 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

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类型 标题 下载最新的英语版本 日期
* 数据表 ADC12C105 12-Bit, 95/105 MSPS A/D Converter 数据表 (Rev. C) 2013年 4月 2日
用户指南 ADC14C105EB and ADC12C105EB Evaluation Board User Guide (Rev. A) 2013年 10月 11日
EVM 用户指南 ADC16DV160HFEB Evaluation Board User Guide 2012年 1月 25日

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