ADC11DS105
- Clock Duty Cycle Stabilizer
- Single +3.0 or +3.3V Supply Operation
- Serial LVDS Outputs
- Serial Control Interface
- Overrange Outputs
- 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
Key Specifications
- Resolution 11 Bits
- Conversion Rate 105 MSPS
- SNR (fIN = 240 MHz) 66 dBFS (typ)
- SFDR (fIN = 240 MHz) 82 dBFS (typ)
- Full Power Bandwidth 1 GHz (typ)
- Power Consumption 1 W (typ)
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The ADC11DS105is a high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 11-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. The ADC11DS105 may be operated from a single +3.0 or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC11DS105 can be operated with an external 1.2V reference. The selectable duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the internal registers for full control of the ADC11DS105's functionality. The ADC11DS105 is available in a 60-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | ADC11DS105 Dual 11-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs 数据表 (Rev. C) | 2013年 4月 2日 |
设计和开发
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封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
WQFN (NKA) | 60 | Ultra Librarian |
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