产品详情

Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 2000 Architecture Folding Interpolating SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 55.5 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 2000 Architecture Folding Interpolating SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 55.5 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CFP (NBC) 128 382.515364 mm² 19.558 x 19.558
  • Total Ionizing Dose 300 krad(Si)
  • Single Event Latch-up 120 MeV-cm2/mg
  • Single +1.9V ±0.1V Operation
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment
  • Choice of SDR or DDR output clocking
  • 1:1 or 1:2 Selectable Output Demux
  • Second DCLK output
  • Duty Cycle Corrected Sample Clock
  • Test pattern
  • Serial Interface for Extended Control

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Code Error Rate 10-18 (typ)
  • ENOB at 748 MHz Input 7.2 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating in 1:2 Demux Output 2.0 W (typ)
    • Power Down Mode 2.9 mW (typ)

All trademarks are the property of their respective owners.

  • Total Ionizing Dose 300 krad(Si)
  • Single Event Latch-up 120 MeV-cm2/mg
  • Single +1.9V ±0.1V Operation
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment
  • Choice of SDR or DDR output clocking
  • 1:1 or 1:2 Selectable Output Demux
  • Second DCLK output
  • Duty Cycle Corrected Sample Clock
  • Test pattern
  • Serial Interface for Extended Control

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Code Error Rate 10-18 (typ)
  • ENOB at 748 MHz Input 7.2 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating in 1:2 Demux Output 2.0 W (typ)
    • Power Down Mode 2.9 mW (typ)

All trademarks are the property of their respective owners.

The ADC08D1520 is an 8–Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 2.9 mW in the Power Down Mode and is available in a 128-pin, thermally enhanced, multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range.

The ADC08D1520 is an 8–Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 2.9 mW in the Power Down Mode and is available in a 128-pin, thermally enhanced, multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 13
类型 标题 下载最新的英语版本 日期
* 数据表 ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter 数据表 (Rev. O) 2013年 3月 19日
* 辐射与可靠性报告 ADC SEU Test Method 2012年 5月 4日
* 辐射与可靠性报告 ADC08D1520WGFQV SEU Report 2012年 5月 4日
* 辐射与可靠性报告 ADC08D1520WGFQV TID Report 2012年 5月 4日
* 辐射与可靠性报告 Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
更多文献资料 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
应用手册 单粒子效应置信区间计算 (Rev. A) PDF | HTML 下载英文版本 (Rev.A) PDF | HTML 2022年 12月 2日
应用手册 重离子轨道环境单粒子效应估算 (Rev. A) PDF | HTML 下载英文版本 (Rev.A) PDF | HTML 2022年 11月 30日
电子书 电子产品辐射手册 (Rev. B) 2022年 5月 7日
选择指南 TI Space Products (Rev. I) 2022年 3月 3日
电子书 电子产品辐射手册 (Rev. A) 2019年 5月 21日
应用手册 AN-1558 Clocking High-Speed A/D Converters (Rev. B) 2013年 5月 1日
应用手册 Application Note 1558 Clocking High-Speed A/D Converters (cn) 2007年 3月 17日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

仿真模型

ADC08D1520QML IBIS Model

SNAM008.ZIP (19 KB) - IBIS Model
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 引脚 下载
CFP (NBC) 128 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频